1. Field
This disclosure relates to generating connections for testing a network or network device.
2. Description of the Related Art
In many types of communications networks, each message to be sent is divided into portions of fixed or variable length. Each portion may be referred to as a packet, a frame, a cell, a datagram, a data unit, or other unit of information, all of which are referred to herein as packets.
Each packet contains a portion of an original message, commonly called the payload of the packet. The payload of a packet may contain data, or may contain voice or video information. The payload of a packet may also contain network management and control information. In addition, each packet contains identification and routing information, commonly called a packet header. The packets are sent individually over the network through multiple switches or nodes. The packets are reassembled into the message at a final destination using the information contained in the packet headers, before the message is delivered to a target device or end user. At the receiving end, the reassembled message is passed to the end user in a format compatible with the user's equipment.
Communications networks that transmit messages as packets are called packet switched networks. Packet switched networks commonly contain a mesh of transmission paths which intersect at hubs or nodes. At least some of the nodes may include a switching device or router that receives packets arriving at the node and retransmits the packets along appropriate outgoing paths. Packet switched networks are governed by a layered structure of industry-standard protocols.
Layer 1 protocols define the physical (electrical, optical, or wireless) interface between nodes of the network. Layer 1 protocols include various Ethernet physical configurations, the Synchronous Optical Network (SONET) and other optical connection protocols, and various wireless protocols such as Wi-Fi.
Layer 2 protocols govern how data is logically transferred between nodes of the network. Layer 2 protocols include the Ethernet, Asynchronous Transfer Mode (ATM), Frame Relay, and Point to Point Protocol (PPP).
Layer 3 protocols govern how packets are routed from a source to a destination along paths connecting multiple nodes of the network. The dominant layer 3 protocols are the well-known Internet Protocol version 4 (IPv4) and version 6 (IPv6). A packet switched network may need to route IP packets using a mixture of the Ethernet, ATM, FR, and/or PPP layer 2 protocols. At least some of the nodes of the network may include a router that extracts a destination address from a network layer header contained within each packet. The router then used the destination address to determine the route or path along which the packet should be retransmitted. A typical packet may pass through a plurality of routers, each of which repeats the actions of extracting the destination address and determining the route or path along which the packet should be retransmitted.
In order to test a packet switched network or a device included in a packet switched communications network, test traffic comprising a large number of packets may be generated, transmitted into the network at one or more ports, and received at different ports. In this context, the term “port” refers to a communications connection between the network and the equipment used to test the network. The term “port unit” refers to a module within the network test equipment that connects to the network at a port. The received test traffic may be analyzed to measure the performance of the network. Each port unit connected to the network may be a source of test traffic, a destination for test traffic, or both a source of and a destination for test traffic. Each port unit may emulate a plurality of logical source or destination addresses. The number of port units and the communications paths that connect the port units to the network are typically fixed for the duration of a test session. The internal structure of the network may change during a test session, for example due to failure of a communications path or hardware device.
For the purpose of collecting test data, the test traffic for each traffic item may be organized into packet groups, where a “packet group” is any plurality of packets for which network traffic statistics are accumulated. The packets in a given packet group may be distinguished by a packet group identifier (PGID) contained in each packet. The PGID may be, for example, a dedicated identifier field or combination of two or more fields within each packet.
For the purpose of reporting network traffic data, the test traffic for each traffic item may be organized into flows, where a “flow” is any plurality of packets for which network traffic statistics are reported. Each flow may consist of a single packet group or a small plurality of packet groups. Each packet group may typically belong to a single flow.
Within this description, the term “logic circuit” means a collection of hardware, which may be augmented by firmware and/or software, which performs a described function or set of functions. The term “logic circuit” encompasses combinatorial logic and sequential logic such as, for example, state machines. All or portions of a “logic circuit” may be implemented by a micro-controller or other processor. Logic circuits may typically be designed using a hardware description language (HDL) that defines the logic circuits primarily in functional terms. The HDL design may be verified using an HDL simulation tool. The verified HDL design may then be converted into a gate netlist or other physical description of the logic circuits in a process commonly termed “synthesis”. The synthesis may be performed automatically using a synthesis tool. The gate netlist or other physical description may be converted into process instructions and masks for fabricating the engine within an application specific integrated circuit (ASIC).
A gate netlist or other physical description of logic circuits may be further converted into configuration data for implementing the logic circuits in a field programmable gate array (FPGA), a programmable logic device (PLD), or a programmable logic arrays (PLA), or other programmable semiconductor device, all of which will be referred to herein as “programmable circuit devices”. Configuration data for programming a programmable circuit device may be stored in a memory or a machine readable storage medium and used to configure a programmable circuit device upon power-up of a test system. In this patent, the term “machine readable storage medium” means a non-volatile medium for storing digital data. Examples of machine readable storage media include optical discs such as CD-ROM, CD-RW, and DVD discs; magnetic medium such as hard and flexible magnetic discs and magnetic tape; and nonvolatile semiconductor devices such as read-only and flash memories. The term “machine readable storage medium” is not intended to encompass transitory media such as signals and waveforms that may convey digital data.
Within this description, a hardware “unit” also means a collection of hardware, which may be augmented by firmware and/or software, which may be on a larger scale or have a more focused function than a “logic circuit”. The terms “logic circuit” and “unit” do not imply any physical separation or demarcation. All or portions of one or more logic circuits and/or units may be collocated on a common card, such as a network card or within a common programmable device, ASIC, or other circuit device.
Throughout this description, elements appearing in figures are assigned three-digit reference designators, where the most significant digit is the figure number where the element is introduced and the two least significant digits are specific to the element. An element that is not described in conjunction with a figure may be presumed to have the same characteristics and function as a previously-described element having the same reference designator.
In block diagrams, arrow-terminated lines may indicate data paths rather than signals. Each data path may be multiple bits in width. For example, each data path may consist of 4, 8, 16, 64, 256, or more parallel connections.